(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a metal-insulator-metal (MIM), capacitor structure for a dynamic random access memory (DRAM), device.
(2) Description of Prior Art
The ability to merge DRAM arrays with logic circuits require complex process integration, in addition to the process difficulties encountered as a result of the topology created by the DRAM capacitor structures. The formation of crown shaped, DRAM capacitor structures, prior to formation of first level metal interconnections, require thick insulator layers to successfully cover the topology created by the DRAM capacitor structures. However the use of thick insulator layers, needed for coverage of the DRAM capacitor structures, requires the use for high aspect ratio contact openings, in the logic region. The use of high aspect ratio contact holes present process difficulties in terms of dry etching through the thick insulator layers, as well as difficulties encountered during the metal filling of the narrow diameter, deep openings. These process difficulties can result in yield loss for the logic chips comprised with embedded DRAM arrays. This invention will describe a fabrication process in which DRAM arrays are embedded in logic circuits, however with the DRAM devices featuring the use of a damascene procedure to fabricate a metal-insulator-metal (MIM), DRAM capacitor structure, thus alleviating the severe topology, and the process difficulties associated with this topology, created when using conventional crown shaped, DRAM capacitor structures. Prior art, such as Lee et al, in U.S. Pat. No. 5,918,135, as well as Nishikawa et al, in U.S. Pat. No. 6,087,261, describe the fabrication of MIM capacitor structures, however these prior arts do not describe the integration of embedded DRAM arrays with logic circuits, and do not describe the novel damascene process, described in the present invention, which allows reduced topology to be realized, thus reducing process complexity, for embedded DRAM array designs.